| AND_GATE Project Status | |||
| Project File: | and_gate.ise | Current State: | Placed and Routed |
| Module Name: | and_gate |
|
No Errors |
| Target Device: | xc3s250e-4tq144 |
|
2 Warnings |
| Product Version: | ISE 9.1.03i |
|
Wed Jun 20 16:14:14 2007 |
| AND_GATE Partition Summary | |||
| No partition information was found. |
| Device Utilization Summary | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of 4 input LUTs | 1 | 4,896 | 1% | |
| Logic Distribution | ||||
| Number of occupied Slices | 1 | 2,448 | 1% | |
| Number of Slices containing only related logic | 1 | 1 | 100% | |
| Number of Slices containing unrelated logic | 0 | 1 | 0% | |
| Total Number of 4 input LUTs | 1 | 4,896 | 1% | |
| Number of bonded IOBs | 3 | 108 | 2% | |
| Total equivalent gate count for design | 6 | |||
| Additional JTAG gate count for IOBs | 144 | |||
| Performance Summary | |||
| Final Timing Score: | 0 | Pinout Data: | Pinout Report |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
| Timing Constraints: | All Constraints | ||
| Detailed Reports | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos |
| Synthesis Report | Current | Tue Jun 12 15:48:19 2007 | 0 | 0 | 0 |
| Translation Report | Current | Tue Jun 12 21:42:32 2007 | 0 | 0 | 0 |
| Map Report | Current | Tue Jun 12 21:42:55 2007 | 0 | 2 Warnings | 2 Infos |
| Place and Route Report | Current | Tue Jun 12 21:43:10 2007 | 0 | 0 | 1 Info |
| Static Timing Report | Current | Tue Jun 12 21:43:14 2007 | 0 | 0 | 3 Infos |
| Bitgen Report | |||||