Xilinx Design Summary

HEARTBEAT Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	18	4,896	1%
Number of 4 input LUTs	3	4,896	1%
Logic Distribution
Number of occupied Slices	11	2,448	1%
Number of Slices containing only related logic	11	11	100%
Number of Slices containing unrelated logic	0	11	0%
Total Number of 4 input LUTs	20	4,896	1%
Number used as logic	3
Number used as a route-thru	17
Number of bonded IOBs	3	108	2%
Number of GCLKs	2	24	8%
Number of DCMs	1	4	25%
Total equivalent gate count for design	7,270
Additional JTAG gate count for IOBs	144

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met