Xilinx Design Summary

SRAM_TEST Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	57	4,896	1%
Number of 4 input LUTs	40	4,896	1%
Logic Distribution
Number of occupied Slices	48	2,448	1%
Number of Slices containing only related logic	48	48	100%
Number of Slices containing unrelated logic	0	48	0%
Total Number of 4 input LUTs	74	4,896	1%
Number used as logic	40
Number used as a route-thru	34
Number of bonded IOBs	30	108	27%
IOB Flip Flops	10
Number of GCLKs	4	24	16%
Number of DCMs	2	4	50%
Total equivalent gate count for design	15,025
Additional JTAG gate count for IOBs	1,440

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met