Xilinx Design Summary

USB_LOOPBACK Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	62	4,896	1%
Number of 4 input LUTs	46	4,896	1%
Logic Distribution
Number of occupied Slices	52	2,448	2%
Number of Slices containing only related logic	52	52	100%
Number of Slices containing unrelated logic	0	52	0%
Total Number of 4 input LUTs	80	4,896	1%
Number used as logic	46
Number used as a route-thru	34
Number of bonded IOBs	42	108	38%
IOB Flip Flops	20
Number of GCLKs	4	24	16%
Number of DCMs	2	4	50%
Total equivalent gate count for design	15,205
Additional JTAG gate count for IOBs	2,016

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met